pieddemamouth wrote:Why did you have choose "AVCC with external capacitor at AREF pin" for the voltage reference ... I have use "AREF, Internal Vref turned off" for the voltage reference.
Since the AREF pin is connected to AVCC you can use either setting, it should give the same result.
- Why did you have selected the "ADC Prescaler". To my mind it's useless, we want the ADC result asap.
The ADC
can't be run at the full 16MHz processor clock speed - some prescaling is essential. According to the Atmel data sheet:
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
My prescaler setting of 6 gives a divide-by-64 so the ADC clock rate will be 125kHz.
Out of interest I just tried adding a second ADC routine to my test code with a different prescaler setting, displaying the results of the two routines. A prescaler setting of 5 (divide-by-32) seems to work fine, even though the 250kHz ADC clock speed is slightly higher than recommended, but a prescaler setting of 4 (divide-by-16) or less gives jittery results.
I wouldn't worry about speeding up the ADC conversion, however, as voltage doesn't change very quickly. It would be better to modify the ADC routine to prevent the processor having to wait for the result, e.g. use an interrupt to grab the result from the ADC when it's ready, or simply allow the processor to go away and do some other stuff and come back for the result later. My little ADC routine can definitely be improved...
Kess
pieddemamouth wrote:Why did you have choose "AVCC with external capacitor at AREF pin" for the voltage reference ... I have use "AREF, Internal Vref turned off" for the voltage reference.
Since the AREF pin is connected to AVCC you can use either setting, it should give the same result.
- Why did you have selected the "ADC Prescaler". To my mind it's useless, we want the ADC result asap.
The ADC
can't be run at the full 16MHz processor clock speed - some prescaling is essential. According to the Atmel data sheet:
By default, the successive approximation circuitry requires an input clock frequency between 50kHz and 200kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
My prescaler setting of 6 gives a divide-by-64 so the ADC clock rate will be 125kHz.
Out of interest I just tried adding a second ADC routine to my test code with a different prescaler setting, displaying the results of the two routines. A prescaler setting of 5 (divide-by-32) seems to work fine, even though the 250kHz ADC clock speed is slightly higher than recommended, but a prescaler setting of 4 (divide-by-16) or less gives jittery results.
I wouldn't worry about speeding up the ADC conversion, however, as voltage doesn't change very quickly. It would be better to modify the ADC routine to prevent the processor having to wait for the result, e.g. use an interrupt to grab the result from the ADC when it's ready, or simply allow the processor to go away and do some other stuff and come back for the result later. My little ADC routine can definitely be improved...
Kess